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"Productive Hardware Designs using Hybrid HLS-RTL Development."

Blaise Tine et al. (2020)

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DOI: 10.1145/3373087.3375338

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-04

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  dblp key:
  - conf/fpga/TineLVK20
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  - https://dblp.org/rec/conf/fpga/TineLVK20
Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim:
Productive Hardware Designs using Hybrid HLS-RTL Development. FPGA 2020: 311

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