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"Circuit design of a dual-versioning L1 data cache for optimistic concurrency."

Azam Seyedi et al. (2011)

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DOI: 10.1145/1973009.1973074

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-02

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  - conf/glvlsi/SeyediACUHV11
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  - https://dblp.org/rec/conf/glvlsi/SeyediACUHV11
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330

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