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ORCID"On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate ..."
Ming-Dou Ker et al. (2009)
- Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang:
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. ISCAS 2009: 2281-2284
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