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"Efficient STT-RAM last-level-cache architecture to replace DRAM cache."

Fazal Hameed, Christian Menard, Jerónimo Castrillón (2017)

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DOI: 10.1145/3132402.3132414

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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  dblp key:
  - conf/memsys/HameedMC17
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Fazal Hameed, Christian Menard, Jerónimo Castrillón:
Efficient STT-RAM last-level-cache architecture to replace DRAM cache. MEMSYS 2017: 141-151

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