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"SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype."

Chad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim (2015)

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DOI: 10.1145/2818950.2818954

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/memsys/KerseyYK15
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  - https://dblp.org/rec/conf/memsys/KerseyYK15
Chad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim:
SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. MEMSYS 2015: 29-30

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