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"A Novel Test Generation Method for Small-Delay Defects with User-Defined ..."

Chao-Jun Shang et al. (2019)

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DOI: 10.1109/VLSI-DAT.2019.8741773

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-27

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  dblp key:
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  - https://dblp.org/rec/conf/vlsi-dat/ShangWLC19
Chao-Jun Shang, Cheng-Hung Wu, Kuen-Jong Lee, Yu-Hsiang Chen:
A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model. VLSI-DAT 2019: 1-4

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