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"2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with ..."

Mark A. Anders et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502333

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-25

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Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. VLSI Circuits 2018: 39-40

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