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"High-Speed Serializing/De-Serializing Design-For-Test Method for ..."

David F. Heidel et al. (1998)

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DOI: 10.1109/VTEST.1998.670873

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vts/HeidelDHINSS98
David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238

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