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"Design and performance evaluation of a systolic architecture for ..."

Venkatramana G. Ajjanagadde, Lalit M. Patnaik (1988)

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DOI: 10.1016/0097-8493(88)90010-6

access: closed

type: Journal Article

metadata version: 2020-02-19

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  - https://dblp.org/rec/journals/cg/AjjanagaddeP88
Venkatramana G. Ajjanagadde, Lalit M. Patnaik:
Design and performance evaluation of a systolic architecture for hidden-surface removal. Comput. Graph. 12(1): 71-74 (1988)

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