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"Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout."

Shusuke Yoshimoto et al. (2013)

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DOI: 10.1587/TRANSFUN.E96.A.1579

access: closed

type: Journal Article

metadata version: 2024-03-11

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  dblp key:
  - journals/ieicet/YoshimotoONKY13
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/YoshimotoONKY13
Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1579-1585 (2013)

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