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"A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy ..."

Yuan-Ho Chen et al. (2014)

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DOI: 10.1142/S0218126614500741

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - https://dblp.org/rec/journals/jcsc/ChenLSLO14
Yuan-Ho Chen, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou:
A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique. J. Circuits Syst. Comput. 23(5) (2014)

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