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ORCID"A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS."
Viki Szortyka et al. (2015)
- Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk
, Piet Wambacq:
A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. IEEE J. Solid State Circuits 50(9): 2025-2036 (2015)
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