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"Integrating physical level design and high level synthesis for ..."

Deepak Kachave, Anirban Sengupta (2016)

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DOI: 10.1016/J.MICROREL.2016.03.006

access: closed

type: Journal Article

metadata version: 2020-02-22

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Deepak Kachave, Anirban Sengupta:
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. Microelectron. Reliab. 60: 141-152 (2016)

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