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"General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing."

Foad Dabiri et al. (2008)

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DOI: 10.1109/TCAD.2008.2003268

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/DabiriNMPS08
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  - https://dblp.org/rec/journals/tcad/DabiriNMPS08
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh:
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1788-1797 (2008)

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