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"A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) ..."

Chao Fan et al. (2019)

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DOI: 10.1109/TCSI.2019.2936226

access: closed

type: Journal Article

metadata version: 2020-08-06

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Chao Fan, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4850-4861 (2019)

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