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"Delay Analysis for Current Mode Threshold Logic Gate Designs."

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas (2017)

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DOI: 10.1109/TVLSI.2016.2608953

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/DaraHT17
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for Current Mode Threshold Logic Gate Designs. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1063-1071 (2017)

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