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ORCID"Design and FPGA-Implementation of a High Performance Timing Recovery Loop ..."
Vicente Torres-Carot et al. (2009)
- Vicente Torres-Carot
, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J. Signal Process. Syst. 56(1): 17-23 (2009)
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