"Detection of false paths in logical circuits by joint analysis of the ..."

Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh (2013)

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DOI: 10.1134/S0005117913070084

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type: Journal Article

metadata version: 2020-07-03

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Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh:
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. 74(7): 1164-1177 (2013)

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