"A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode ..."

Hyeonsik Kim, Soohoon Lee, Jintae Kim (2023)

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DOI: 10.1109/ACCESS.2023.3248784

access: open

type: Journal Article

metadata version: 2023-03-28

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Hyeonsik Kim, Soohoon Lee, Jintae Kim:
A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers. IEEE Access 11: 22531-22541 (2023)

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