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"A graph partitioning heuristic for the parallel pseudo-exhaustive logical ..."

Alexandre A. Andreatta, Celso C. Ribeiro (1994)

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DOI: 10.1007/BF02085633

access: closed

type: Journal Article

metadata version: 2022-04-09

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Alexandre A. Andreatta, Celso C. Ribeiro:
A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits. Ann. Oper. Res. 50(1): 1-36 (1994)

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