"An Efficient Hardware Accelerator for Structured Sparse Convolutional ..."

Chaoyang Zhu et al. (2020)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2020-01-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-2001-01955
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  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-2001-01955
Chaoyang Zhu, Kejie Huang, Shuyuan Yang, Ziqi Zhu, Hejia Zhang, Haibin Shen:
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs. CoRR abs/2001.01955 (2020)

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