"Python-based DSL for generating Verilog model of Synchronous Digital Circuits."

Mandar Datar et al. (2024)

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DOI: 10.48550/ARXIV.2406.09208

access: open

type: Informal or Other Publication

metadata version: 2024-07-09

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  - https://dblp.org/rec/journals/corr/abs-2406-09208
Mandar Datar, Dhruva S. Hegde, Vendra Durga Prasad, Manish Prajapati, Neralla Manikanta, Devansh Gupta, Janampalli Pavanija, Pratyush Pare, Akash, Shivam Gupta, Sachin B. Patkar:
Python-based DSL for generating Verilog model of Synchronous Digital Circuits. CoRR abs/2406.09208 (2024)

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