"VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning ..."

Patrick Yubeaton et al. (2025)

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DOI: 10.48550/ARXIV.2505.20302

access: open

type: Informal or Other Publication

metadata version: 2025-06-27

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  - journals/corr/abs-2505-20302
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  - https://dblp.org/rec/journals/corr/abs-2505-20302
Patrick Yubeaton, Andre Nakkab, Weihua Xiao, Luca Collini, Ramesh Karri, Chinmay Hegde, Siddharth Garg:
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification. CoRR abs/2505.20302 (2025)

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