"Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage."

Junius Pun et al. (2025)

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DOI: 10.48550/ARXIV.2507.11709

access: open

type: Informal or Other Publication

metadata version: 2025-08-17

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  - journals/corr/abs-2507-11709
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  - https://dblp.org/rec/journals/corr/abs-2507-11709
Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah:
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. CoRR abs/2507.11709 (2025)

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