"Design of an Area Efficient and High-Performance Adder with a Novel Sum ..."

Niyas Ahamed Allavudeen et al. (2024)

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DOI: 10.1007/S00034-024-02724-Z

access: closed

type: Journal Article

metadata version: 2024-10-06

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  - https://dblp.org/rec/journals/cssp/AllavudeenMKS24
Niyas Ahamed Allavudeen, Madheswaran Muthusamy, Anand Karuppannan, Nazrin Salma Sheriff:
Design of an Area Efficient and High-Performance Adder with a Novel Sum Generator. Circuits Syst. Signal Process. 43(9): 5897-5911 (2024)

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