"A 2-20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay ..."

Yinghao Chen et al. (2024)

> Home

Details and statistics

DOI: 10.1007/S00034-023-02473-5

access: closed

type: Journal Article

metadata version: 2024-01-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/ChenCFZZH24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/ChenCFZZH24
Yinghao Chen, Yingmei Chen, Wentian Fan, Qingyi Zhao, En Zhu, Zhengfei Hu:
A 2-20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop. Circuits Syst. Signal Process. 43(1): 318-330 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.