"In-Memory Computing with 6T SRAM for Multi-operator Logic Design."

Narendra Singh Dhakad et al. (2024)

> Home

Details and statistics

DOI: 10.1007/S00034-023-02481-5

access: closed

type: Journal Article

metadata version: 2024-08-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/DhakadCRSV24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/DhakadCRSV24
Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma:
In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst. Signal Process. 43(1): 646-660 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.