"Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit ..."

Saeid Gorgin, Ghassem Jaberipur, Reza Hashemi Asl (2014)

> Home

Details and statistics

DOI: 10.1007/S00034-014-9823-4

access: closed

type: Journal Article

metadata version: 2022-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/GorginJA14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/GorginJA14
Saeid Gorgin, Ghassem Jaberipur, Reza Hashemi Asl:
Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers. Circuits Syst. Signal Process. 33(12): 3883-3899 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.