"A New Circuit-Level Technique for Leakage and Short-Circuit Power ..."

Mohammad Moradinezhad Maryan, Majid Amini Valashani, Seyed Javad Azhari (2021)

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DOI: 10.1007/S00034-020-01639-9

access: closed

type: Journal Article

metadata version: 2021-07-13

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  - https://dblp.org/rec/journals/cssp/MaryanVA21
Mohammad Moradinezhad Maryan, Majid Amini Valashani, Seyed Javad Azhari:
A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology. Circuits Syst. Signal Process. 40(7): 3536-3560 (2021)

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