"Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for ..."

Rohan Mukherjee et al. (2017)

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DOI: 10.1007/S00034-016-0315-6

access: closed

type: Journal Article

metadata version: 2020-06-21

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  - https://dblp.org/rec/journals/cssp/MukherjeeBCDSR17
Rohan Mukherjee, Baishik Biswas, Indrajit Chakrabarti, Pranab Kumar Dutta, Somnath Sengupta, Ajoy Kumar Ray:
Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of (512×512) Frames. Circuits Syst. Signal Process. 36(2): 640-657 (2017)

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