"An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the ..."

Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar (2020)

> Home

Details and statistics

DOI: 10.1007/S00034-020-01411-Z

access: closed

type: Journal Article

metadata version: 2024-02-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/PrasadPT20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/PrasadPT20
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks. Circuits Syst. Signal Process. 39(10): 5247-5271 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.