"Built-in Self Test Power and Test Time Analysis in On-chip Networks."

Mahdieh Nadi Senejani et al. (2015)

> Home

Details and statistics

DOI: 10.1007/S00034-014-9892-4

access: closed

type: Journal Article

metadata version: 2020-10-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/SenejaniGOM15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/SenejaniGOM15
Mahdieh Nadi Senejani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad Nadzir Marsono:
Built-in Self Test Power and Test Time Analysis in On-chip Networks. Circuits Syst. Signal Process. 34(4): 1057-1075 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.