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"A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency ..."

Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed Chaudhry (2016)

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DOI: 10.1007/S00034-015-0201-7

access: closed

type: Journal Article

metadata version: 2020-06-21

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  - journals/cssp/ShabbirGC16
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  - https://dblp.org/rec/journals/cssp/ShabbirGC16
Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed Chaudhry:
A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm. Circuits Syst. Signal Process. 35(9): 3113-3134 (2016)

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