"A versatile hardware architecture for a constant false alarm rate ..."

Roberto Perez-Andrade et al. (2010)

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DOI: 10.1016/J.DSP.2010.02.001

access: closed

type: Journal Article

metadata version: 2020-02-20

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  - https://dblp.org/rec/journals/dsp/Perez-AndradeCUC10
Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digit. Signal Process. 20(6): 1733-1747 (2010)

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