"RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern ..."

Saeyeon Kim et al. (2025)

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DOI: 10.1109/LES.2025.3600611

access: closed

type: Journal Article

metadata version: 2025-11-09

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Saeyeon Kim, Sunyoung Park, Nahyeon Kim, Jiyoung Lee, Ji-Hoon Kim:
RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern Generation. IEEE Embed. Syst. Lett. 17(5): 333-336 (2025)

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