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"An Approach to Minimize the Test Configuration for the Logic Cells of the ..."

Michel Renovell et al. (2000)

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DOI: 10.1023/A:1008355701933

access: closed

type: Journal Article

metadata version: 2021-12-24

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Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. 16(3): 289-299 (2000)

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