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"Hierarchical Modeling of the VLSI Design Process."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Amir K. Hekmatpour, Alex Orailoglu, Paul M. Chau (1991)

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DOI: 10.1109/64.79710

access: closed

type: Journal Article

metadata version: 2017-05-26

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Amir K. Hekmatpour, Alex Orailoglu, Paul M. Chau:
Hierarchical Modeling of the VLSI Design Process. IEEE Expert 6(2): 56-70 (1991)

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last updated on 2017-05-26 22:50 CEST by the dblp team

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