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"Performance-Driven Architectural Synthesis for Distributed Register-File ..."

Juinn-Dar Huang et al. (2012)

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DOI: 10.1587/TRANSFUN.E95.A.559

access: closed

type: Journal Article

metadata version: 2020-06-15

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  - https://dblp.org/rec/journals/ieicet/HuangCHLJ12
Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou:
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 559-566 (2012)

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