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"An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on ..."

Kenji Kanazawa, Tsutomu Maruyama (2017)

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DOI: 10.1587/TRANSINF.2016EDP7487

access: closed

type: Journal Article

metadata version: 2020-04-11

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  dblp key:
  - journals/ieicet/KanazawaM17
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/KanazawaM17
Kenji Kanazawa, Tsutomu Maruyama:
An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA. IEICE Trans. Inf. Syst. 100-D(8): 1807-1818 (2017)

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