"A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing ..."

Kazutoshi Kobayashi et al. (2007)

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DOI: 10.1093/IETELE/E90-C.10.1919

access: closed

type: Journal Article

metadata version: 2020-04-11

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Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(10): 1919-1926 (2007)

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