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"A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted ..."

Hyunui Lee et al. (2013)

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DOI: 10.1587/TRANSFUN.E96.A.422

access: closed

type: Journal Article

metadata version: 2022-10-02

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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/LeeAMM13
Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa:
A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 422-433 (2013)

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