"A VLSI Architecture with Multiple Fast Store-Based Block Parallel ..."

Kazuhiro Nakamura et al. (2012)

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DOI: 10.1587/TRANSELE.E95.C.456

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type: Journal Article

metadata version: 2020-12-29

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  - https://dblp.org/rec/journals/ieicet/NakamuraSYTT12
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Trans. Electron. 95-C(4): 456-467 (2012)

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