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"Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for ..."

Yuichi Nakamura, Takeshi Yoshimura (2006)

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DOI: 10.1093/IETFEC/E89-A.12.3458

access: closed

type: Journal Article

metadata version: 2023-03-10

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Yuichi Nakamura, Takeshi Yoshimura:
Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3458-3463 (2006)

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