"Chip-Level Performance Improvement Using Triple Damascene Wiring Design ..."

Noriaki Oda et al. (2006)

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DOI: 10.1093/IETELE/E89-C.11.1544

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type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/OdaKKTTTI06
Noriaki Oda, Hiroyuki Kunishima, Takashi Kyouno, Kazuhiro Takeda, Tomoaki Tanaka, Toshiyuki Takewaki, Masahiro Ikeda:
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond. IEICE Trans. Electron. 89-C(11): 1544-1550 (2006)

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