"A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip ..."

Yusuke Ohtomo et al. (2008)

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DOI: 10.1093/IETELE/E91-C.4.655

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type: Journal Article

metadata version: 2020-04-11

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Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa:
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI. IEICE Trans. Electron. 91-C(4): 655-661 (2008)

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