"Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor."

Jinli Rao et al. (2018)

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DOI: 10.1587/TRANSINF.2017ICP0019

access: closed

type: Journal Article

metadata version: 2020-04-11

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Jinli Rao, Tianyong Ao, Shu Xu, Kui Dai, Xuecheng Zou:
Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor. IEICE Trans. Inf. Syst. 101-D(11): 2698-2705 (2018)

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