"An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based ..."

Nobutaro Shibata, Mitsuo Nakamura (2018)

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DOI: 10.1587/TRANSFUN.E101.A.1185

access: closed

type: Journal Article

metadata version: 2020-04-11

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Nobutaro Shibata, Mitsuo Nakamura:
An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(8): 1185-1196 (2018)

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