"An Integrated Timing and Dynamic Supply Noise Verification for ..."

Kenji Shimazaki et al. (2006)

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DOI: 10.1093/IETELE/E89-C.11.1535

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type: Journal Article

metadata version: 2020-04-11

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Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa:
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Trans. Electron. 89-C(11): 1535-1543 (2006)

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