"Power-Efficient LDPC Decoder Architecture Based on Accelerated ..."

Kazunori Shimizu et al. (2006)

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DOI: 10.1093/IETFEC/E89-A.12.3602

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type: Journal Article

metadata version: 2020-10-26

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Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3602-3612 (2006)

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