"Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current ..."

Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin (2010)

> Home

Details and statistics

DOI: 10.1587/TRANSFUN.E93.A.2581

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  authority control:
- export record
  dblp key:
  - journals/ieicet/WuKL10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/WuKL10
Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin:
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2581-2589 (2010)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.